FIELD OF THE INVENTION
The invention lies in the semiconductor technology field. More specifically, the invention relates to a semiconductor memory with memory banks, which can be selected by associated memory bank decoders.
Memory cells in semiconductor memories are arranged in matrix form, that is to say in rows and columns. Address decoders are in each case provided for rows and columns, and allow one of the rows or columns to be selected. Normally, the memory cells are activated in rows via word lines by switching on access transistors via which in each case one capacitor is accessed, in which the information in the memory cell is stored. The line path of the transistors is connected in columns to bit lines via which the information in a memory cell can be read, after having been amplified with a read amplifier. Access for writing information to be stored to a memory cell takes place in a corresponding manner.
In very modern semiconductor memories using dynamic memory cells (DRAMs), the memory cell array has a bank architecture.
A memory bank contains all those functional units which are required to carry out a memory access autonomously. A memory bank is thus assigned respective row and column address decoders, together with read amplifiers and other functional units required for operation of the semiconductor memory, for example time control circuits, redundancy circuits etc. If necessary, functional units in different memory banks may be used jointly, for example read amplifiers or bit line or column decoders.
A memory bank and the functional units associated with it are activated by memory bank decoders. When access to a specific memory cell in a memory bank is intended, the functional units associated with the memory bank are switched from a waiting state or standby to an activated state. The actuation process is brought about by a memory bank decoder output signal associated with that memory bank. Each memory bank has a unique memory bank address assigned to it. When the address is applied to the memory bank decoder, the output signal of the latter associated with the memory bank is activated.
As the number of memory banks increases, the memory bank decoders become more complex. By way of example, a DRAM with a memory capacity of 64 Mbits comprises 16 memory banks, and a DRAM with 128 Mbits and a corresponding architecture comprises 32 memory banks.